PerfSuite Hardware Performance Summary Report Version : 1.0 Created : Mon Dec 30 11:31:53 AM Central Standard Time 2002 Generator : psprocess 0.5 XML Source : /u/ncsa/anyuser/performance/psrun-ia64.xml Execution Information ============================================================================================ Date : Sun Dec 15 21:01:20 2002 Host : user01 Processor and System Information ============================================================================================ Node CPUs : 2 Vendor : Intel Family : IPF Model : Itanium CPU Revision : 6 Clock (MHz) : 800.136 Memory (MB) : 2007.16 Pagesize (KB): 16 Cache Information ============================================================================================ Cache levels : 3 -------------------------------- Level 1 Type : data Size (KB) : 16 Linesize (B) : 32 Assoc : 4 Type : instruction Size (KB) : 16 Linesize (B) : 32 Assoc : 4 -------------------------------- Level 2 Type : unified Size (KB) : 96 Linesize (B) : 64 Assoc : 6 -------------------------------- Level 3 Type : unified Size (KB) : 4096 Linesize (B) : 64 Assoc : 4 Index Description Counter Value ============================================================================================ 1 Conditional branch instructions mispredicted..................... 4831072449 2 Conditional branch instructions correctly predicted.............. 52023705122 3 Conditional branch instructions taken............................ 47366258159 4 Floating point instructions...................................... 86124489172 5 Total cycles..................................................... 594547754568 6 Instructions completed........................................... 1049339828741 7 Level 1 data cache accesses...................................... 30238866204 8 Level 1 data cache hits.......................................... 972479062 9 Level 1 data cache misses........................................ 29224377672 10 Level 1 instruction cache reads.................................. 221828591306 11 Level 1 cache misses............................................. 29312740738 12 Level 2 data cache accesses...................................... 129470315862 13 Level 2 data cache misses........................................ 15569536443 14 Level 2 data cache reads......................................... 110524791561 15 Level 2 data cache writes........................................ 18622708948 16 Level 2 instruction cache reads.................................. 566330907 17 Level 2 store misses............................................. 1208372120 18 Level 2 cache misses............................................. 15401180750 19 Level 3 data cache accesses...................................... 4650999018 20 Level 3 data cache hits.......................................... 186108211 21 Level 3 data cache misses........................................ 4451199079 22 Level 3 data cache reads......................................... 4613582451 23 Level 3 data cache writes........................................ 38456570 24 Level 3 instruction cache misses................................. 3631385 25 Level 3 instruction cache reads.................................. 17631093 26 Level 3 cache misses............................................. 4470968725 27 Load instructions................................................ 111438431677 28 Load/store instructions completed................................ 130391246662 29 Cycles Stalled Waiting for memory accesses....................... 256484777623 30 Store instructions............................................... 18840914540 31 Cycles with no instruction issue................................. 61889609525 32 Data translation lookaside buffer misses......................... 2832692 Event Index ============================================================================================ 1: PAPI_BR_MSP 2: PAPI_BR_PRC 3: PAPI_BR_TKN 4: PAPI_FP_INS 5: PAPI_TOT_CYC 6: PAPI_TOT_INS 7: PAPI_L1_DCA 8: PAPI_L1_DCH 9: PAPI_L1_DCM 10: PAPI_L1_ICR 11: PAPI_L1_TCM 12: PAPI_L2_DCA 13: PAPI_L2_DCM 14: PAPI_L2_DCR 15: PAPI_L2_DCW 16: PAPI_L2_ICR 17: PAPI_L2_STM 18: PAPI_L2_TCM 19: PAPI_L3_DCA 20: PAPI_L3_DCH 21: PAPI_L3_DCM 22: PAPI_L3_DCR 23: PAPI_L3_DCW 24: PAPI_L3_ICM 25: PAPI_L3_ICR 26: PAPI_L3_TCM 27: PAPI_LD_INS 28: PAPI_LST_INS 29: PAPI_MEM_SCY 30: PAPI_SR_INS 31: PAPI_STL_ICY 32: PAPI_TLB_DM Statistics ============================================================================================ Graduated instructions per cycle....................................... 1.765 Graduated floating point instructions per cycle........................ 0.145 % graduated floating point instructions of all graduated instructions.. 8.207 Graduated loads/stores per cycle....................................... 0.219 Graduated loads/stores per graduated floating point instruction........ 1.514 Mispredicted branches per correctly predicted branch................... 0.093 Level 1 data cache accesses per graduated instruction.................. 2.882 Graduated floating point instructions per level 1 data cache access.... 2.848 Level 1 cache line reuse (data)........................................ 3.462 Level 2 cache line reuse (data)........................................ 0.877 Level 3 cache line reuse (data)........................................ 2.498 Level 1 cache hit rate (data).......................................... 0.776 Level 2 cache hit rate (data).......................................... 0.467 Level 3 cache hit rate (data).......................................... 0.714 Level 1 cache miss ratio (instruction)................................. 0.003 Level 1 cache miss ratio (data)........................................ 0.966 Level 2 cache miss ratio (data)........................................ 0.120 Level 3 cache miss ratio (data)........................................ 0.957 Bandwidth used to level 1 cache (MB/s)................................. 1262.361 Bandwidth used to level 2 cache (MB/s)................................. 1326.512 Bandwidth used to level 3 cache (MB/s)................................. 385.087 % cycles with no instruction issue..................................... 10.410 % cycles stalled on memory access...................................... 43.139 MFLOPS (cycles)........................................................ 115.905 MFLOPS (wallclock)..................................................... 114.441 MIPS (cycles).......................................................... 1412.190 MIPS (wallclock)....................................................... 1394.349 CPU time (seconds)..................................................... 743.058 Wall clock time (seconds).............................................. 752.566 % CPU utilization...................................................... 98.737