Finding Out Machine Information

psinv is a PerfSuite command-line utility that can be used to gather information about a processor and available resources.

psinv is available on x86, x86-64, and ia64 platforms.

psinv is particularly useful/convenient for those who are doing performance analysis with PAPI, either directly or through other PerfSuite software such as psrun.

Manual Page



psinv - PerfSuite machine information utility  


psinv [ -h | -f | -p | -v | -V ]  


psinv is a command-line utility that displays information about your computer and available hardware performance events.  


Describe features of CPU (IA-32 only).
Provide brief help on usage
List available PAPI events (if PerfSuite was configured with PAPI support).
Show all available information.
Report psinv version.


Please refer to the file share/perfsuite/doc/BUGS for information about known bugs in psinv.  




Rick Kufrin  


University of Illinois/NCSA Open Source License




Example Use

The easiest way to learn to use psinv is simply to run it. Here's an example of the type of information returned by psinv:

titan:~3% psinv -v
System Information -
Processors:             2
Total Memory:           2007.16 MB
System Page Size:       16.00 KB

Processor Information -
Vendor:                 Intel
Processor family:       IPF
Model (Type):           Itanium
Revision:               6
Clock Speed:            800.136 MHz

Cache and TLB Information -
Cache levels:           3
Caches/TLBs:            7

Cache Details -
Level 1:
        Type:           Data
        Size:           16 KB
        Line size:      32 bytes
        Associativity:  4-way set associative

        Type:           Instruction
        Size:           16 KB
        Line size:      32 bytes
        Associativity:  4-way set associative

Level 2:
        Type:           Unified
        Size:           96 KB
        Line size:      64 bytes
        Associativity:  6-way set associative

Level 3:
        Type:           Unified
        Size:           4.00 MB
        Line size:      64 bytes
        Associativity:  4-way set associative

TLB Details -
Level 1:
        Type:           Data
        Entries:        32
        Pagesize (KB):  4 8 16 64 256 1024 4096 16384 65536 262144
        Associativity:  32-way set associative

        Type:           Instruction
        Entries:        64
        Pagesize (KB):  4 8 16 64 256 1024 4096 16384 65536 262144
        Associativity:  64-way set associative

Level 2:
        Type:           Data
        Entries:        96
        Pagesize (KB):  4 8 16 64 256 1024 4096 16384 65536 262144
        Associativity:  96-way set associative

PAPI Standard Event Information -
Standard events:	43
Non-derived events:	26
Derived events:		17

PAPI Standard Event Details -
        PAPI_BR_INS:    Branch instructions
        PAPI_BR_PRC:    Conditional branch instructions correctly predicted
        PAPI_L1_DCA:    Level 1 data cache accesses
        PAPI_L1_DCM:    Level 1 data cache misses
        PAPI_L1_ICM:    Level 1 instruction cache misses
        PAPI_L2_DCA:    Level 2 data cache accesses
        PAPI_L2_DCR:    Level 2 data cache reads
        PAPI_L2_DCW:    Level 2 data cache writes
        PAPI_L2_ICM:    Level 2 instruction cache misses
        PAPI_L2_STM:    Level 2 store misses
        PAPI_L2_TCM:    Level 2 cache misses
        PAPI_L3_DCR:    Level 3 data cache reads
        PAPI_L3_DCW:    Level 3 data cache writes
        PAPI_L3_ICH:    Level 3 instruction cache hits
        PAPI_L3_ICM:    Level 3 instruction cache misses
        PAPI_L3_ICR:    Level 3 instruction cache reads
        PAPI_L3_STM:    Level 3 store misses
        PAPI_L3_TCM:    Level 3 cache misses
        PAPI_LD_INS:    Load instructions
        PAPI_MEM_SCY:   Cycles Stalled Waiting for memory accesses
        PAPI_SR_INS:    Store instructions
        PAPI_STL_ICY:   Cycles with no instruction issue
        PAPI_TLB_DM:    Data translation lookaside buffer misses
        PAPI_TLB_IM:    Instruction translation lookaside buffer misses
        PAPI_TOT_CYC:   Total cycles
        PAPI_TOT_INS:   Instructions completed
        PAPI_BR_MSP:    Conditional branch instructions mispredicted
        PAPI_BR_NTK:    Conditional branch instructions not taken
        PAPI_BR_TKN:    Conditional branch instructions taken
        PAPI_FLOPS:     Floating point instructions per second
        PAPI_FP_INS:    Floating point instructions
        PAPI_L1_DCH:    Level 1 data cache hits
        PAPI_L1_ICR:    Level 1 instruction cache reads
        PAPI_L1_LDM:    Level 1 load misses
        PAPI_L1_TCM:    Level 1 cache misses
        PAPI_L2_DCM:    Level 2 data cache misses
        PAPI_L2_ICR:    Level 2 instruction cache reads
        PAPI_L2_LDM:    Level 2 load misses
        PAPI_L3_DCA:    Level 3 data cache accesses
        PAPI_L3_DCH:    Level 3 data cache hits
        PAPI_L3_DCM:    Level 3 data cache misses
        PAPI_L3_LDM:    Level 3 load misses
        PAPI_LST_INS:   Load/store instructions completed

National Center for Supercomputing Applications
University of Illinois at Urbana-Champaign